Three dimensional wafer level chip scale packaging (3D-WLCSP) is a technology in development that has potential for significant benefits in the mobile and radio frequency (RF) fields. However, there is a poor heat transfer path from the chips or packages mounted on top of the fan out WLCSP package to the printed circuit board (PCB), which is the primary heat transfer path for mobile applications due to the absence of airflow and restrictions of heat sinks.
Conventional processes have attempted to address heat transfer problems. With some processes, an electrically insulating material is placed around a chip and encapsulated in a mold compound. The electrical vias are formed in the electrically insulating material instead of the mold compound. Other processes utilize a leadframe based wirebond assembly, with exposed heat spreader pins that extend from the bottom side of the package. Wire bonding is required for input/output (I/O). Additional processes utilize leadframe based flip chip assembly with a heat spreader providing a direct thermal path from a center to an exposed bottom package surface. Other processes utilize through mold vias (TMV) between chips stacked on top and the PCB. However, these conventional processes do not provide sufficient thermal transfer pathways.
A need therefore exists for methodology enabling improved thermal transfer between top packages and the PCB and the resulting device.